ATEMGA128L View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128L' PDF : 395 Pages View PDF
System Clock and
Clock Options
Clock Systems and their
Distribution
Figure 18 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 44. The clock systems
are detailed below.
Figure 18. Clock Distribution
Asynchronous
Timer/Counter
General I/O
modules
ADC
CPU Core
RAM
Flash and
EEPROM
clkI/O
clkASY
clkADC
AVR Clock
Control Unit
clkCPU
clkFLASH
Reset Logic
Watchdog Timer
Source clock
Clock
Multiplexer
Watchdog clock
Watchdog
Oscillator
CPU Clock – clkCPU
I/O Clock – clkI/O
Flash Clock – clkFLASH
Timer/Counter
Oscillator
External RC
Oscillator
External clock
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Reg-
ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that address recognition in the TWI
module is carried out asynchronously when clkI/O is halted, enabling TWI address recep-
tion in all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
36 ATmega128
2467O–AVR–10/06
Share Link: 
