ATF-531P8-TR1 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
ATF-531P8-TR1
Avago Technologies
'ATF-531P8-TR1' PDF : 15 Pages View PDF
ATF-531P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4V and Ids = 135 mA unless otherwise specified.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Vgs
Operational Gate Voltage Vds = 4V, Ids = 135 mA
V
—
0.68
—
Vth
Threshold Voltage Vds = 4V, Ids = 8 mA
V
—
0.3
—
Idss
Saturated Drain Current Vds = 4V, Vgs = 0V
µA
—
3.7
—
Gm
Transconductance Vds = 4.5V, Gm = ∆Idss/∆Vgs; mmho —
∆Vgs = Vgs1 - Vgs2
Vgs1 = 0.6V, Vgs2 = 0.55V
650
—
Igss
Gate Leakage Current Vds = 0V, Vgs = -4V
µA -10 -0.34
—
NF
Noise Figure[1] f = 2 GHz
f = 900 MHz
dB
—
0.6
1
dB
—
0.6
—
G
Gain[1] f = 2 GHz
f = 900 MHz
dB
18.5
20
21.5
dB
—
25
—
OIP3
Output 3rd Order f = 2 GHz
Intercept Point[1,2] f = 900 MHz
dBm
35.5
38
—
dBm
—
37
—
P1dB
Output 1dB f = 2 GHz
Compressed[1] f = 900 MHz
dBm
—
dBm
—
24.5
—
23
—
PAE
Power Added Efficiency f = 2 GHz
f = 900 MHz
%
—
57
—
%
—
45
—
ACLR
Adjacent Channel Leakage Offset BW = 5 MHz
Power Ratio[1,3] Offset BW = 10 MHz
dBc
— -68
—
dBc
— -64
—
Notes:
1. Measurements obtained using production test board described in Figure 6.
2. F1 = 2.00 GHz, F2 = 2.01 GHz and Pin = -10 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
– Test Model 1
– Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
– Freq = 2140 MHz
– Pin = -5 dBm
– Chan Integ Bw = 3.84 MHz
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.66
Γ_ang = -165°
(1.8 dB loss)
Output
Matching Circuit
DUT
Γ_mag = 0.09
Γ_ang = 118°
(1.1 dB loss)
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-
off between optimal OIP3, NF and VSWR. Circuit losses have been de-embedded from actual measurements.
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