ATF1504ASL-25AI44 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATF1504ASL-25AI44' PDF : 35 Pages View PDF
Output AC Test Loads
ATF1504AS(L)
Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
Power-down Mode
The ATF1504AS includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a high-Z state at the
onset will remain at high-Z. During power-down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Power Down AC Characteristics(1)(2)
-7
Symbol Parameter
Min Max
tIVDH
Valid I, I/O before PD High
7
tGVDH
Valid OE(2) before PD High
7
tCVDH
Valid Clock(2) before PD High
7
tDHIX
I, I/O Don’t Care after PD High
12
tDHGX
OE(2) Don’t Care after PD High
12
tDHCX
Clock(2) Don’t Care after PD High
12
tDLIV
PD Low to Valid I, I/O
1
tDLGV
PD Low to Valid OE (Pin or Term)
1
tDLCV
PD Low to Valid Clock (Pin or Term)
1
tDLOV
PD Low to Valid Output
1
Notes: 1. For slow slew outputs, add tSSO.
2. Pin or product term.
3. Includes tRPA due to reduced power bit enabled.
-10
Min Max
10
10
10
15
15
15
1
1
1
1
-15
Min Max
15
15
15
25
25
25
1
1
1
1
-20
Min Max
20
20
20
30
30
30
1
1
1
1
-25
Min Max
25
25
25
35
35
35
1
1
1
1
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
15
0950O–PLD–7/05
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