ATF1504BE View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATF1504BE' PDF : 30 Pages View PDF
12. Power-down Mode
The ATF1504BE includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 100 µA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file or through Atmel software. Designs using the
power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
Table 12-1. Power-down AC Characteristics(1)(2)
Symbol Parameter
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
tDLGV
tDLCV
tDLOV
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
Notes: 1. For low-drive outputs, add tSSO.
2. Pin or product term.
-5/-7
Min
Max
10
10
10
5
5
5
2
2
2
2
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
22 ATF1504BE
3637B–PLD–1/08
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