ATMEGA128 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128' PDF : 395 Pages View PDF
2467O–AVR–10/06
ATmega128
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-
face is enabled, this pin can not be used as an I/O pin.
• ADC3 – ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal
Name PF7/ADC7/TDI
PF6/ADC6/TDO
PF5/ADC5/TMS
PUOE JTAGEN
JTAGEN
JTAGEN
PUOV 1
0
1
DDOE JTAGEN
JTAGEN
JTAGEN
DDOV 0
SHIFT_IR +
0
SHIFT_DR
PVOE 0
JTAGEN
0
PVOV 0
TDO
0
DIEOE JTAGEN
JTAGEN
JTAGEN
DIEOV 0
0
0
DI
–
–
–
AIO
TDI/ADC7 INPUT ADC6 INPUT
TMS/ADC5
INPUT
PF4/ADC4/TCK
JTAGEN
1
JTAGEN
0
0
0
JTAGEN
0
–
TCKADC4 INPUT
Table 44. Overriding Signals for Alternate Functions in PF3..PF0
Signal Name
PF3/ADC3
PF2/ADC2
PF1/ADC1
PUOE
0
0
0
PUOV
0
0
0
DDOE
0
0
0
DDOV
0
0
0
PVOE
0
0
0
PVOV
0
0
0
DIEOE
0
0
0
DIEOV
0
0
0
DI
–
–
–
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
PF0/ADC0
0
0
0
0
0
0
0
0
–
ADC0 INPUT
83
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