ATmega128
Definitions
Timer/Counter Clock
Sources
Counter Unit
operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select
logic block controls which clock source the Timer/Counter uses to increment (or decre-
ment) its value. The Timer/Counter is inactive when no clock source is selected. The
output from the clock select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the wave-
form generator to generate a PWM or variable frequency output on the Output Compare
Pin (OC0). See “Output Compare Unit” on page 94. for details. The compare match
event will also set the compare flag (OCF0) which can be used to generate an output
compare interrupt request.
Many register and bit references in this document are written in general form. A lower
case “n” replaces the Timer/Counter number, in this case 0. However, when using the
register or bit defines in a program, the precise form must be used (i.e., TCNT0 for
accessing Timer/Counter0 counter value and so on).
The definitions in Table 51 are also used extensively throughout the document.
Table 51. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The
assignment is dependent on the mode of operation.
The Timer/Counter can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clkT0 is by default equal to the MCU clock, clkI/O.
When the AS0 bit in the ASSR Register is written to logic one, the clock source is taken
from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on
asynchronous operation, see “Asynchronous Status Register – ASSR” on page 106. For
details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 109.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 35 shows a block diagram of the counter and its surrounding environment.
Figure 35. Counter Unit Block Diagram
DATA BUS
TOVn
(Int.Req.)
TCNTn
count
clear
Control Logic
direction
clk Tn
Prescaler
T/C
Oscillator
TOSC1
TOSC2
bottom
top
clk
I/O
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