ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
ATmega128
16-bit Timer/Counter
(Timer/Counter1 and
Timer/Counter3)
The 16-bit Timer/Counter unit allows accurate program execution timing (event man-
agement), wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (i.e.,Allows 16-bit PWM)
• Three Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,
OCF3B, OCF3C, and ICF3)
Restrictions in ATmega103
Compatibility Mode
Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available
(Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1
has two Compare Registers (Compare A and Compare B) only.
Overview
Most register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-
pare unit channel. However, when using the register or bit defines in a program, the
precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and
so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the
actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “16-bit Timer/Counter Register Description”
on page 133.
2467O–AVR–10/06
111
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