ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
2467O–AVR–10/06
ATmega128
Table 78. UPMn Bits Settings
UPMn1
UPMn0
0
0
0
1
1
0
1
1
Parity Mode
Disabled
(Reserved)
Enabled, Even Parity
Enabled, Odd Parity
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 79. USBSn Bit Settings
USBSn
0
1
Stop Bit(s)
1-bit
2-bits
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data
bits (character size) in a frame the Receiver and Transmitter use.
Table 80. UCSZn Bits Settings
UCSZn2
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
UCSZn0
0
1
0
1
0
1
0
1
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when Asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCKn).
Table 81. UCPOLn Bit Settings
Transmitted Data Changed (Output of
UCPOLn TxDn Pin)
0
Rising XCKn Edge
1
Falling XCKn Edge
Received Data Sampled (Input on
RxDn Pin)
Falling XCKn Edge
Rising XCKn Edge
193
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