ATMEGA128L-8MC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA128L-8MC' PDF : 395 Pages View PDF
Overview of the TWI
Module
ATmega128
The TWI module is comprised of several submodules, as shown in Figure 94. All regis-
ters drawn in a thick line are accessible through the AVR data bus.
Figure 94. Overview of the TWI Module
SCL
Slew-rate Spike
Control
Filter
SDA
Slew-rate Spike
Control
Filter
Bus Interface Unit
START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Ack
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Scl and SDA Pins
Bit Rate Generator Unit
Bus Interface Unit
2467O–AVR–10/06
Address Match Unit
Address Register
(TWAR)
Address Comparator
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
These pins interface the AVR TWI with the rest of the MCU system. The output drivers
contain a slew-rate limiter in order to conform to the TWI specification. The input stages
contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-
nal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to
the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in
some systems eliminate the need for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-
caler settings, but the CPU clock frequency in the slave must be at least 16 times higher
than the SCL frequency. Note that slaves may prolong the SCL low period, thereby
reducing the average TWI bus clock period. The SCL frequency is generated according
to the following equation:
SCL frequency = --C----P----U------C----l--o---c---k-----f-r--e----q---u---e----n---c---y---
16 + 2(TWBR) ⋅ 4TWPS
• TWBR = Value of the TWI Bit Rate Register
• TWPS = Value of the prescaler bits in the TWI Status Register
Note: Pull-up resistor values should be selected according to the SCL frequency and the
capacitive bus line load. See Table 133 on page 325 for value of pull-up resistor.
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con-
troller and Arbitration detection hardware. The TWDR contains the address or data
bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit
TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be
205
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