ATMEGA261 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATMEGA261' PDF : 226 Pages View PDF
ATtiny261/ATtiny461/ATtiny861
Figure 9-7. Watchdog Timer
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
WATCHDOG
PRESCALER
MCU RESET
9.3 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
9.3.1
Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when disabling an enabled Watch-
dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
desired, but with the WDCE bit cleared.
9.3.2
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
9.4 Register Description
9.4.1
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
Bit
7
6
5
4
3
2
1
0
0x34 (0x54)
–
–
–
–
WDRF
BORF
EXTRF PORF
MCUSR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description
45
7753E–AVR–06/10
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