ATmega32(L)
Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn
OCRn Value
OCFn
Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with
Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
OCRn
TOP - 1
TOP
BOTTOM
TOP
BOTTOM + 1
OCFn
79
2503J–AVR–10/06