ATMEGA64RZAV-10PU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA64RZAV-10PU
Atmel Corporation
'ATMEGA64RZAV-10PU' PDF : 377 Pages View PDF
ATmega644
6.5 Register Description
6.5.1 EEARH and EEARL – The EEPROM Address Register
6.5.2
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
15
–
EEAR7
7
R
R/W
0
X
14
–
EEAR6
6
R
R/W
0
X
13
–
EEAR5
5
R
R/W
0
X
12
–
EEAR4
4
R
R/W
0
X
11
EEAR11
EEAR3
3
R/W
R/W
X
X
10
EEAR10
EEAR2
2
R/W
R/W
X
X
9
EEAR9
EEAR1
1
R/W
R/W
X
X
8
EEAR8
EEAR0
0
R/W
R/W
X
X
EEARH
EEARL
• Bits 15:12 – Res: Reserved Bits
These bits are reserved bits in the ATmega644 and will always read as zero.
• Bits 11:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4
Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
EEDR – The EEPROM Data Register
6.5.3
Bit
0x20 (0x40)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
EEDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
EECR – The EEPROM Control Register
Bit
7
6
5
4
3
2
1
0
0x1F (0x3F)
–
–
EEPM1 EEPM0 EERIE
EEMPE
EEPE
EERE
EECR
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATmega644 and will always read as zero.
• Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 6-1. While EEPE
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
21
2593O–AVR–02/12
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