ATR2406-DEV-KIT2 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATR2406-DEV-KIT2' PDF : 25 Pages View PDF
Table 7-4. PLL Settings of the Main Counter Bits D5 to D6
MC (Main Counter)
D6
D5
SMC
0
0
86
0
1
87
1
0
88
1
1
89
Table 7-5. PLL Settings of the Swallow Counter Bits D0 to D4
SC (Swallow Counter)
D4
D3
D2
D1
D0
SSC
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
2
...
...
...
...
...
...
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
7.6 GFCS Adjustment
The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by
tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are
only relevant in TX mode.
Table 7-6. GFCS Adjustment of Bits D9 - D11
GFCS
D11
D10
D9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
GFCS
60%
70%
80%
90%
100%
110%
120%
130%
12 ATR2406
4779N–ISM–12/08
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