ATSAM3N1BA-AU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAM3N1BA-AU' PDF : 60 Pages View PDF
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in Table 7-3.
Table 7-3.
0
1
2
3
SAM3N Master to Slave Access
Masters
0
Slaves
Cortex-M3 I/D Bus
Internal SRAM
-
Internal ROM
X
Internal Flash
X
Peripheral Bridge
-
1
Cortex-M3 S Bus
X
-
-
X
2
PDC
X
X
-
X
7.6 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4. Peripheral DMA Controller
Instance name
Channel T/R
100 & 64 Pins
TWI0
Transmit
x
UART0
Transmit
x
USART0
Transmit
x
DAC
Transmit
x
SPI
Transmit
x
TWI0
Receive
x
UART0
Receive
x
USART0
Receive
x
ADC
Receive
x
SPI
Receive
x
48 Pins
x
x
x
N/A
x
x
x
x
x
x
28 SAM3N Summary
11011BS–ATARM–22-Feb-12
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