ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
15.8
Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.
This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non
privileged masters still get one latency clock cycle if they need to access the same slave. This technique is used
for masters that mainly perform single accesses or short bursts with some Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever is the number of requesting masters.
15.9
Fixed Default Master
After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave.
All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-
privileged masters will get one latency cycle. This technique is used for a master that mainly performs single
accesses or short bursts with Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput, regardless of the number of requesting masters.
15.10 Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflicts occur, i.e., when two or
more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus
arbitrating each slave specifically.
The Bus Matrix provides the user with the possibility of choosing between two arbitration types or mixing them for
each slave:
Round-robin Arbitration (default)
Fixed Priority Arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
When re-arbitration must be done, specific conditions apply. Refer to Section 15.10.1 “Arbitration Scheduling”.
15.10.1 Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more master requests. In order to avoid burst breaking and
also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following
cycles:
Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently
accessing it.
Single Cycles: when a slave is currently performing a single access.
End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined burst length,
predicted end of burst matches the size of the transfer but is managed differently for undefined burst length.
Refer to Section 15.10.1.1 “Undefined Length Burst Arbitration”.
Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master
access is too long and must be broken. Refer to Section 15.10.1.2 “Slot Cycle Limit Arbitration”.
SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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