ATXMEGA192D3-MH View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATXMEGA192D3-MH' PDF : 109 Pages View PDF
XMEGA D3
Mnemonics
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
Operands
Rd
Description
Rotate Left Through Carry
Rd
Rotate Right Through Carry
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
Operation
Rd(0) ← C,
Rd(n+1) ← Rd(n),
C ← Rd(7)
Rd(7) ← C,
Rd(n) ← Rd(n+1),
C ← Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0) ↔ Rd(7..4)
SREG(s) ← 1
SREG(s) ← 0
I/O(A, b) ← 1
I/O(A, b) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
MCU Control Instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
Flags
Z,C,N,V,H
#Clocks
1
Z,C,N,V
1
Z,C,N,V
1
None
1
SREG(s)
1
SREG(s)
1
None
1
None
1
T
1
None
1
C
1
C
1
N
1
N
1
Z
1
Z
1
I
1
I
1
S
1
S
1
V
1
V
1
T
1
T
1
H
1
H
1
None
1
None
1
None
1
None
1
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
55
8134I–AVR–12/10
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