ATXMEGA384D3-MH View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATXMEGA384D3-MH' PDF : 109 Pages View PDF
XMEGA D3
13. PMIC - Programmable Multi-level Interrupt Controller
13.1 Features
13.2 Overview
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
XMEGA D3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
13.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA D3 devices are
shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are
described for each peripheral in the XMEGA A manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word
address.
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address)
Source
0x000
RESET
0x002
OSCF_INT_vect
0x004
PORTC_INT_base
0x008
PORTR_INT_base
0x014
RTC_INT_base
0x018
TWIC_INT_base
0x01C
TCC0_INT_base
0x028
TCC1_INT_base
0x030
SPIC_INT_vect
0x032
USARTC0_INT_base
0x040
NVM_INT_base
0x044
PORTB_INT_base
0x056
PORTE_INT_base
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E INT base
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8134I–AVR–12/10
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