ATXMEGA384D3-MH View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATXMEGA384D3-MH' PDF : 109 Pages View PDF
3.1 Block Diagram
Figure 3-1. XMEGA D3 Block Diagram
PR[0..1]
XTAL1
XTAL2
XMEGA D3
PA[0..7]
PB[0..7]
PORT A (8)
ACA
ADCA
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
PORT B (8)
Event System
Controller
BUS
Controller
Oscillator
Circuits/
Clock
Generation
Real Time
Counter
Watchdog
Oscillator
Watchdog
Timer
DATA BUS
SRAM
Oscillator
Control
Sleep
Controller
Power
Supervision
POR/BOD &
RESET
Prog/Debug
Controller
PDI
CPU
OCD
Interrupt
Controller
NVM Controller
Flash
EEPROM
USARTF0
TCF0
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PF[0..7]
IRCOM
DATA BUS
EVENT ROUTING NETWORK
PORT C (8)
PC[0..7]
PORT D (8)
PORT E (8)
To Clock
Generator
PD[0..7]
TOSC1
TOSC2
PE[0..7]
5
8134I–AVR–12/10
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