AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Electrical Specifications
4.3
4.4
Processor Clocking
• BCLKP, BCLKN, HPL_CLKINP, HPL_CLKINN, EXP_CLKINP, EXP_CLKINN,
DPL_REFCLKINP, DPL_REFCLKINN
The processor utilizes differential clocks to generate the processor core(s) and uncore
operating frequencies, memory controller frequency, and other internal clocks. The
processor core frequency is determined by multiplying the processor core ratio by 200
MHz. Clock multiplying within the processor is provided by an internal phase locked
loop (PLL), which requires a constant frequency input, with exceptions for Spread
Spectrum Clocking (SSC). PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 4-29 for
DC specifications and to the platform design guide for decoupling and routing
guidelines.
Voltage Identification (VID)
The VID specification for the processor is defined by the Voltage Regulator Down (VRD)
11.0 Design Guidelines. The processor uses seven voltage identification signals,
VID[6:0], to support automatic selection of voltages. Table 4-26 specifies the voltage
level corresponding to the state of VID[6:0]. A ‘1’ in this table refers to a high voltage
level and a ‘0’ refers to a low voltage level. Do take note of the VID pin mapping of the
processor to the VR chip. If the processor is not soldered on board (VID[6:0] =
1111111), or the voltage regulation circuit cannot supply the voltage that is requested,
the voltage regulator must disable itself. Refer to the Voltage Regulator Down (VRD)
11.0 Design Guidelines for further details.
VID signals are CMOS push/pull drivers. Refer to Table 4-33 for the DC specifications
for these signals. Individual processor VID values may be set during manufacturing so
that two devices at the same core frequency may have different VID settings.
The VR utilized must be capable of regulating its output to the value defined by the VID
values issued. DC specifications are included in Table 4-28 and Table 4-29.
VRD11.0 has 8 VID pins (VID[7:0]) compared to 7 VID pins for the processor. VRD11.0
VID[n] pin should be connected to processor VID[n-1] pin. VRD11.0 VID[0] pin should
be tied to Vss. Refer Table 4-27 for mapping details.
38
Datasheet
Share Link: 
