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AV9110-01CS14 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
MFG CO.
AV9110-01CS14
ICST
Integrated Circuit Systems ICST
'AV9110-01CS14' PDF : 10 Pages View PDF
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AV9110
Output Divider Turth Tables
COD1
0
0
1
1
Table 2
COD0
0
1
0
1
CLK/X
Output Divide
(X)
1
2
4
8
COD1
0
0
1
1
Table 3
COD0
0
1
0
1
VCO
Output Divide
(R)
1
2
4
8
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
2 MHz < fREF < 32 MHz
fREF
200 kHz <
< 5MHz
M
50 MHz < f <250 MHz
VCO
fREF = Input reference frequency
M = Reference divide, 3 to 127
f = VCO output frequency
VCO
fVCO < 250 MHz
fCLK = CLK or CLK/X output frequency
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
fVCO =
NVfREF
Where
N = VCO divided, 3 to 127
M
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
fCLK =
fVCO = NVfREF or fREF (output mixable by bit 17)
R
M•R
fCLK/X =
fVCO =
RX
fVCLK
X
Where R, X = output dividers 1, 2, 4 or 8
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
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