AX88772 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'AX88772' PDF : 43 Pages View PDF
8.4.2 Reset Timing
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
XIN12M
RESET_N
Trst
Symbol
Description
Min Typ
Trst Reset pulse width (6ms ~10ms) after XIN12M 72000
-
is running
Max
Units
- XIN12M clock cycle
8.4.3 MII Timing (100Mbps)
Ttclk
Ttch Ttcl
TX_CLK
Tts
Tth
TXD [3:0]
TX_EN, TX_ER
Symbol
Description
Ttclk TX_CLK clock cycle time *1
Ttch TX_CLK clock high time *2
Ttcl TX_CLK clock low time *2
Tts TXD [3:0], TX_EN, TX_ER setup time
Tth TXD [3:0], TX_EN, TX_ER hold time
Min
Typ Max Units
-
40.0
-
ns
-
20.0
-
ns
-
20.0
-
ns
28.0
-
-
ns
5.0
-
-
ns
Trclk Trch Trcl
RX_CLK
RXD [3:0]
Trs
Trh
RX_DV, RX_ER
Symbol
Description
Trclk RX_CLK clock cycle time *1
Trch RX_CLK clock high time *2
Trcl RX_CLK clock low time *2
Trs RXD [3:0], RX_DV, and RX_ER setup time
Trh RXD [3:0], RX_DV, and RX_ER hold time
Min
Typ
-
40.0
-
20.0
-
20.0
3.0
-
0.5
-
*1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns.
*2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns.
Max Units
-
ns
-
ns
-
ns
-
ns
-
ns
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