C8051F040 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F040

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

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C8051F040/1/2/3/4/5/6/7

Table 13.1. Reset Electrical Characteristics

–40 to +85 °C unless otherwise specified.

Parameter

Conditions

RST Output Low Voltage

RST Input High Voltage

IOL = 8.5 mA, VDD = 2.7 V to 3.6 V

RST Input Low Voltage

RST Input Leakage Current

VDD for /RST Output Valid

AV+ for /RST Output Valid

VDD POR Threshold (VRST)

Minimum /RST Low Time to

Generate a System Reset

Reset Time Delay

Missing Clock Detector 

Timeout

RST = 0.0 V

RST rising edge after VDD crosses

VRST threshold

Time from last system clock to

reset initiation

Min

—

0.7 x

VDD

—

—

1.0

1.0

2.40

10

80

100

Typ

—

—

—

50

—

—

2.55

—

100

220

Max

0.6

—

0.3 x

VDD

—

—

—

2.70

—

120

500

Units

V

V

µA

V

V

V

ns

ms

µs

Rev. 1.5

171

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