C8051F064 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F064' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
Figure 6.5. DMA0CF: DMA0 Configuration Register
SFR Page: 3
SFR Address: 0xF8
(bit addressable)
R/W
R
R/W
R/W
DMA0HLT DMA0XBY
-
-
Bit7
Bit6
Bit5
Bit4
R/W
DMA0CIE
Bit3
R/W
DMA0CI
Bit2
R/W
R/W
DMA0EOE DMA0EO
Bit1
Bit0
Reset Value
00000000
Bit 7:
Bit 6:
Bits 5-4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only).
0: DMA0 has complete access to off-chip XRAM.
1: Processor core has complete access to off-chip XRAM. DMA0 will wait until this bit is ‘0’
before writing to off-chip XRAM locations.
DMA0XBY: Off-chip XRAM Busy Flag (C8051F060/2/4/6 Only).
0: DMA0 is not accessing off-chip XRAM.
1: DMA0 is accessing off-chip XRAM.
RESERVED. Write to 00b.
DMA0CIE: Repeat Counter Overflow Interrupt Enable.
0: Disable Repeat Counter Overflow Interrupt.
1: Enable Repeat Counter Overflow Interrupt.
DMA0CI: Repeat Counter Overflow Flag.
0: Repeat Counter Overflow has not occured.
1: Repeat Counter Overflow has occured. This bit must be cleared by software.
DMA0EOE: End-Of-Operation Interrupt Enable.
0: Disable End-Of-Operation Interrupt.
1: Enable End-Of-Operation Interrupt.
DMA0EO: End-Of-Operation Flag.
0: End-Of-Operation Instruction has not been received.
1: End-Of-Operation Instruction has been received. This bit must be cleared by software.
Rev. 1.2
81
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