C8051F302-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F302-GM

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

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C8051F300/1/2/3/4/5

SFR Definition 8.8. IP: Interrupt Priority

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

—

—

PT2

PS0

PT1

PX1

PT0

PX0 11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

(bit addressable) 0xB8

Bits7–6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

UNUSED. Read = 11b, Write = don't care.

PT2: Timer 2 Interrupt Priority Control.

This bit sets the priority of the Timer 2 interrupt.

0: Timer 2 interrupts set to low priority level.

1: Timer 2 interrupts set to high priority level.

PS0: UART0 Interrupt Priority Control.

This bit sets the priority of the UART0 interrupt.

0: UART0 interrupts set to low priority level.

1: UART0 interrupts set to high priority level.

PT1: Timer 1 Interrupt Priority Control.

This bit sets the priority of the Timer 1 interrupt.

0: Timer 1 interrupts set to low priority level.

1: Timer 1 interrupts set to high priority level.

PX1: External Interrupt 1 Priority Control.

This bit sets the priority of the External Interrupt 1 interrupt.

0: External Interrupt 1 set to low priority level.

1: External Interrupt 1 set to high priority level.

PT0: Timer 0 Interrupt Priority Control.

This bit sets the priority of the Timer 0 interrupt.

0: Timer 0 interrupts set to low priority level.

1: Timer 0 interrupts set to high priority level.

PX0: External Interrupt 0 Priority Control.

This bit sets the priority of the External Interrupt 0 interrupt.

0: External Interrupt 0 set to low priority level.

1: External Interrupt 0 set to high priority level.

76

Rev. 2.9

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