C8051F312 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F312' PDF : 224 Pages View PDF
C8051F310/1/2/3/4/5/6/7
Table 9.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
RST Output Low Voltage
IOL = 8.5 mA, VDD = 2.7 to 3.6 V
RST Input High Voltage
Min Typ
—
—
0.7 x
VDD
—
RST Input Low Voltage
—
—
RST Input Pullup Current
RST = 0.0 V
—
25
VDD Monitor Threshold (VRST)
2.40 2.55
Missing Clock Detector Timeout
Time from last system clock rising
edge to reset initiation
100
220
Reset Time Delay
Delay between release of any
reset source and code execution 5.0 —
at location 0x0000
Minimum RST Low Time to
Generate a System Reset
VDD Monitor Turn-on Time
VDD Monitor Supply Current
VDD Ramp Time
VDD = 0 V to VDD = 2.7 V
15 —
100 —
—
20
—
—
Max
0.6
—
0.3 x
VDD
40
2.70
600
—
—
—
50
1
Units
V
V
µA
V
µs
µs
µs
µs
µA
ms
108
Rev. 1.6
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