C8051F312 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F312

8/16 kB ISP Flash MCU Family

Silicon Laboratories 

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C8051F310/1/2/3/4/5/6/7

Table 16.1. SPI Slave Timing Parameters

Parameter

Description

Master Mode Timing* (See Figure 16.8 and Figure 16.9)

TMCKH

SCK High Time

TMCKL

SCK Low Time

TMIS

MISO Valid to SCK Shift Edge

TMIH

SCK Shift Edge to MISO Change

Slave Mode Timing* (See Figure 16.10 and Figure 16.11)

TSE

NSS Falling to First SCK Edge

TSD

Last SCK Edge to NSS Rising

TSEZ

NSS Falling to MISO Valid

TSDZ

NSS Rising to MISO High-Z

TCKH

SCK High Time

TCKL

SCK Low Time

TSIS

MOSI Valid to SCK Sample Edge

TSIH

SCK Sample Edge to MOSI Change

TSOH

SCK Shift Edge to MISO Change

TSLH

Last SCK Edge to MISO Change

(CKPHA = 1 ONLY)

Min

1 x TSYSCLK

1 x TSYSCLK

1 x TSYSCLK + 20

0

Max

—

—

—

—

Units

ns

ns

ns

ns

2 x TSYSCLK

2 x TSYSCLK

—

—

5 x TSYSCLK

5 x TSYSCLK

2 x TSYSCLK

2 x TSYSCLK

—

6 x TSYSCLK

—

ns

—

ns

4 x TSYSCLK ns

4 x TSYSCLK ns

—

ns

—

ns

—

ns

—

ns

4 x TSYSCLK ns

8 x TSYSCLK ns

*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).

Rev. 1.6

181

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