C8051F327 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F327' PDF : 141 Pages View PDF
C8051F326/7
6. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
two 16-bit counter/timers (see description in Section “14. Timers” on page 127), an enhanced full-duplex
UART (see description in Section “13. UART0” on page 117), 256 bytes of internal RAM, 128 byte Special
Function Register (SFR) address space (Section “6.2.6. Special Function Registers” on page 43), and 15
Port I/O (see description in Section “11. Port Input/Output” on page 79). The CIP-51 also includes on-chip
debug hardware (see description in Section “15. C2 Interface” on page 135), and interfaces directly with
the USB and other digital subsystems providing a complete solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 6.1 for a block diagram).
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction
- 15 Port I/O
Set
- Extended Interrupt Handler
- 25 MIPS Peak Throughput with 25 MHz
- Reset Input
Clock
- Power Management Modes
- 0 to 25 MHz Clock Frequency
- On-chip Debug Logic
- 256 Bytes of Internal RAM
- Program and Data Memory Security
DATA BUS
ACCUMULATOR
TMP1
TMP2
PSW
ALU
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
SFR_ADDRESS
SFR
SFR_CONTROL
D8
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
RESET
CLOCK
CONTROL
LOGIC
PIPELINE
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
A16
INTERFACE MEM_WRITE_DATA
MEM_READ_DATA
D8
INTERRUPT
INTERFACE
D8
SYSTEM_IRQs
EMULATION_IRQ
Figure 6.1. CIP-51 Block Diagram
Rev. 1.1
35
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