C8051F327 View Datasheet(PDF) - Silicon Laboratories
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MFG CO.
'C8051F327' PDF : 141 Pages View PDF
C8051F326/7
6.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 6.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 6.3, for a detailed description of each register.
Table 6.2. Special Function Register (SFR) Memory Map
F8
F0
B
E8
E0 ACC
D8
D0 PSW
C8
REG0CN
C0
B8
IP
CLKMUL
B0 P3
A8
IE
CLKSEL
A0 P2
98 SCON0 SBUF0
90
SBCON0
88 TCON
TMOD
80 P0
SP
0(8)
1(9)
(bit addressable)
GPIOCN
OSCICN
EMI0CN
SMOD0
TL0
DPL
2(A)
OSCLCN
OSCICL
P0MDOUT
SBRLL0
TL1
DPH
3(B)
SBRLH0
TH0
4(C)
TH1
5(D)
EIP1
EIE1
VDM0CN
EIP2
RSTSRC
EIE2
USB0XCN
FLSCL
FLKEY
P2MDOUT P3MDOUT
USB0ADR
CKCON
6(E)
USB0DAT
PSCTL
PCON
7(F)
Table 6.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address
Description
ACC
0xE0
Accumulator
B
0xF0
B Register
CKCON
0x8E
Clock Control
CLKMUL
0x91
Clock Multiplier
CLKSEL
0xA9
Clock Select
DPH
0x83
Data Pointer High
DPL
0x82
Data Pointer Low
EIE1
0xE6
Extended Interrupt Enable 1
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