C8051F326/7
Table 7.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
‘F326 RST Output Voltage
‘F327 RST Output Voltage
RST Input High Voltage*
Conditions
Min Typ
IOL = –8.5 mA; VIO = 2.7 to 3.6 V
—
—
IOL = –8.5 mA; VIO = 2.0 V;
IOL = –8.5 mA; VIO = 2.7 to 3.6 V
—
—
0.7 x VIO —
Max Units
0.6
V
0.6
0.6
V
—
V
RST Input Low Voltage*
—
— 0.3 x VIO V
‘F326 RST Pullup Current
10
26
40
µA
‘F327 RST Pullup Current
—
26
40
µA
VDD Monitor Threshold (VRST)
2.40 2.55 2.70
V
Missing Clock Detector Timeout Time from last system clock rising 100 240 500
µs
edge to reset initiation
Reset Time Delay
Delay between the release of any 5.0
—
—
µs
reset source and code execution
at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
VDD Monitor Turn-on Time
100
—
—
µs
VDD Monitor Supply Current
—
20
50
µA
*Note: On 'F327 devices, VIO = VDD.
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Rev. 1.1