C8051F337 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F337' PDF : 227 Pages View PDF
C8051F336/7/8/9
SFR Definition 7.1. ADC0CF: ADC0 Configuration
Bit
7
Name
Type
Reset
1
6
5
4
AD0SC[4:0]
R/W
1
1
1
SFR Address = 0xBC
3
2
1
0
AD0LJST
R/W
R
R
1
0
0
0
Bit
Name
Function
7:3
AD0SC[4:0]
ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the fol-
lowing equation, where AD0SC refers to the 5-bit value held in
bits AD0SC4–0. SAR Conversion clock requirements are given
in the ADC specification table.
AD0SC = S----Y----S----C----L---K--- – 1
CLKSAR
2
AD0LJST
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
1:0
UNUSED
Unused. Read = 00b; Write = don’t care.
Rev.1.0
41
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