C8051F344 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F344' PDF : 276 Pages View PDF
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A Power-On Reset delay (TPORDelay) occurs before the device is released from reset; this delay is
typically less than 0.3 ms. Figure 11.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
2.70
2.4
VRST
VDD
2.0
1.0
t
RST
Logic HIGH
Logic LOW
TPORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 11.2. Power-On and VDD Monitor Reset Timing
Rev. 1.3
101
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