C8051F346 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F346' PDF : 276 Pages View PDF
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 13.1. AC Parameters for External Memory Interface
Parameter
Description
Min*
TACS
TACW
TACH
TALEH
Address / Control Setup Time
Address / Control Pulse Width
Address / Control Hold Time
Address Latch Enable High Time
0
1 x TSYSCLK
0
1 x TSYSCLK
TALEL
TWDS
Address Latch Enable Low Time
Write Data Setup Time
1 x TSYSCLK
1 x TSYSCLK
TWDH
Write Data Hold Time
0
TRDS
Read Data Setup Time
20
TRDH
Read Data Hold Time
0
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Max*
3 x TSYSCLK
16 x TSYSCLK
3 x TSYSCLK
4 x TSYSCLK
4 x TSYSCLK
19 x TSYSCLK
3 x TSYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
130
Rev. 1.3
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