C8051F350 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F350' PDF : 234 Pages View PDF
C8051F350/1/2/3
14.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above
VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 14.2.
plots the power-on and VDD monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
delay (TPORDelay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from
reset before VDD reaches the VRST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following
a power-on reset.
VDD
2.70
V
2.55
RST
2.0
1.0
t
/RST
Logic HIGH
Logic LOW
TPORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 14.2. Power-On and VDD Monitor Reset Timing
116
Rev. 1.1
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