C8051F352 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F352' PDF : 234 Pages View PDF
C8051F350/1/2/3
Table 5.3. ADC0 Electrical Characteristics
VDD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz,
Decimation Ratio = 1920, –40 to +85 °C unless otherwise noted.
Parameter
24-bit ADC (C8051F350/1)
Resolution
No Missing Codes
16-bit ADC (C8051F352/3)
Resolution
No Missing Codes
All Devices
Conditions
Integral Nonlinearity
Offset Error (Calibrated)
Offset Drift vs. Temperature
Gain Error (Calibrated)
Gain Drift vs. Temperature
Modulator Clock (MDCLK)
Modulator Sampling Frequency
Output Word Rate
Analog Inputs
Analog Input Voltage Range
(AIN+ – AIN–)
PGA Gain = 1, Bipolar
PGA Gain = 1, Unipolar
Absolute Voltage on AIN+ or AIN–
pin with respect to AGND
Input Buffers OFF
Input Current
Input Buffer ON
Input Impedance
Input Buffer OFF,
Gain = 1
Common Mode Rejection Ratio
DC
50/60 Hz
Input Buffers
PGA Gain = 1, 2, 4, or 8
High Buffer Input Range with respect
PGA Gain = 16
to AGND
PGA Gain = 32
PGA Gain = 64 or 128
PGA Gain = 1, 2, 4, or 8
Low Buffer Input Range with respect
PGA Gain = 16
to AGND
PGA Gain = 32
PGA Gain = 64 or 128
Burnout Current Sources
Positive (AIN+) Channel Current
VREF = 2.5 V
Negative (AIN–) Channel Current
VREF = 2.5 V
Min
—
—
—
—
—
—
—
–VREF
0
0
—
—
95
1.4
1.45
1.5
1.6
0.1
0.15
0.2
0.25
0.9
–0.9
Typ
Max
24
24
16
16
—
±15
±5
—
10
—
±0.002
—
±0.5
—
2.4576
—
MDCLK/128
—
1000
—
—
—
± 1.5
7
110
100
+VREF
+VREF
AV+
30
—
—
—
—
AV+ – 0.1
— AV+ – 0.15
—
AV+ – 0.2
— AV+ – 0.25
—
AV+ – 1.4
— AV+ – 1.45
—
AV+ – 1.5
—
AV+ – 1.6
2
2.9
–2
–2.9
Units
bits
bits
bits
bits
ppm
FS
ppm
nV/
°C
%
ppm/
°C
MHz
Hz
sps
V
V
nA
MΩ
dB
dB
V
V
V
V
V
V
V
V
µA
µA
Rev. 1.1
61
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