C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F362-GM2' PDF : 288 Pages View PDF
C8051F360/1/2/3/4/5/6/7/8/9
5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)
The ADC0 subsystem for the C8051F360/1/2/6/7/8/9 consists of two analog multiplexers (referred to col-
lectively as AMUX0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion
modes, and window detector are all configurable under software control via the Special Function Registers
shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured
to measure P1.0-P3.4 (where available), the Temperature Sensor output, or VDD with respect to P1.0-
P3.4, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control reg-
ister (ADC0CN) is set to logic ‘1’. The ADC0 subsystem is in low power shutdown when this bit is logic ‘0’.
P1.0-1.3 available on
C8051F361/2/6/7/8/9
P1.0
P1.7
P2.0
P3.1-3.4 available on
C8051F360/1/6/8
Temp
Sensor
P2.7
P3.0
P3.4
VDD
P1.0-1.3 available on
C8051F361/2/6/7/8/9
P1.0
P1.7
P2.0
P3.1-3.4 available on
C8051F360/1/6/8
P2.7
P3.0
P3.4
VREF
GND
23-to-1
AMUX
AMX0P
23-to-1
AMUX
AMX0N
ADC0CN
VDD
000
Start
Conversion
001
010
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
011
Timer 1 Overflow
100
CNVSTR Input
10-Bit
(+)
SAR
101
Timer 3 Overflow
(-)
ADC
ADC0CF
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
AD0WINT
Window
Compare
32
Logic
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.0
47
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