C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F362-GM2' PDF : 288 Pages View PDF
C8051F360/1/2/3/4/5/6/7/8/9
SFRPAGE
pushed to
SFRNEXT
SFR Page 0x00
Automatically
pushed on stack in
SFRPAGE on ADC0
interrupt
0x00
(ADC0)
0x0F
(OSCICN)
SFRPAGE
SFRNEXT
SFRLAST
Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs
While in the ADC0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the ADC0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place SFR page 0x00 into the
SFRPAGE register. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 0x00
for ADC0) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register
before the PCA interrupt (in this case SFR Page 0x0F for OSCICN) is pushed down to the SFRLAST reg-
ister, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the
SFRLAST register) will be overwritten. See Figure 9.6 below.
SFRPAGE
pushed to
SFRNEXT
SFRNEXT
pushed to
SFRLAST
SFR Page 0x00
Automatically
pushed on stack in
SFRPAGE on PCA
interrupt
0x00
(PCA)
0x00
(ADC0)
0x0F
(OSCICN)
SFRPAGE
SFRNEXT
SFRLAST
Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR
Rev. 1.0
91
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