C8051F365-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F365-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

Prev 101 102 103 104 105 106 107 108 109 110 Next

C8051F360/1/2/3/4/5/6/7/8/9

Table 10.1. Interrupt Summary (Continued)

Interrupt Source

Interrupt

Vector

Priority

Order

Pending Flag

Enable

Flag

Priority

Control

Programmable Counter

Array

Comparator0

Comparator1

Timer 3 Overflow

RESERVED

Port Match

0x005B

0x0063

0x006B

0x0073

0x007B

0x0083

11

CF (PCA0CN.7)

CCFn (PCA0CN.n)

YN

EPCA0

(EIE1.4)

PPCA0

(EIP1.4)

12

CP0FIF (CPT0CN.4)

CP0RIF (CPT0CN.5)

N

N

ECP0

(EIE1.5)

PCP0

(EIP1.5)

13

CP1FIF (CPT1CN.4)

CP1RIF (CPT1CN.5)

N

N

ECP1

(EIE1.6)

PCP1

(EIP1.6)

14

TF3H (TMR3CN.7)

TF3L (TMR3CN.6)

NN

ET3

(EIE1.7)

PT3

(EIP1.7)

15 N/A

N/A N/A N/A

N/A

16 N/A

N/A N/A

EMAT

(EIE2.1)

PMAT

(EIP2.1)

10.4. Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the

data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt

conditions for the peripheral and the behavior of its interrupt-pending flag(s).

Rev. 1.0

109

Share Link: