C8051F374 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F374' PDF : 300 Pages View PDF
C8051F39x/37x
9.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of three SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to
initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion
begins on the rising edge of CNVSTR. See Figure 9.2 for track and convert timing details. Tracking can
also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time require-
ments described in Section “9.2.3. Settling Time Requirements” on page 52.
CNVSTR
(AD0CM[2:0]=100)
SAR Clocks
A. ADC0 Timing for External Trigger Source
1
2
3
4
5
6
7
8
9
1
0
1
1
AD0TM=1
Low Power
or Convert
Track
Convert
Low Power
Mode
AD0TM=0
Track or Convert
Convert
Track
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
SAR
Clocks
AD0TM=1
B. ADC0 Timing for Internal Trigger Source
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
Low Power
or Convert
Track
Convert
Low Power Mode
SAR
Clocks
AD0TM=0
1
2
3
4
5
6
7
8
9
1
0
1
1
Track or
Convert
Convert
Track
Figure 9.2. 10-Bit ADC Track and Conversion Example Timing
Preliminary Rev. 0.71
51
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