C8051F380 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F380' PDF : 321 Pages View PDF
C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.13. CMINT: USB0 Common Interrupt
Bit
7
6
5
4
3
2
1
0
Name
SOF
RSTINT RSUINT SUSINT
Type
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x06
Bit Name
Function
7:4 Unused Read = 0000b. Write = don’t care.
3
SOF Start of Frame Interrupt Flag.
Set by hardware when a SOF token is received. This interrupt event is synthesized by
hardware: an interrupt will be generated when hardware expects to receive a SOF
event, even if the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
2 RSTINT Reset Interrupt-Pending Flag.
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
1 RSUINT Resume Interrupt-Pending Flag.
Set by hardware when Resume signaling is detected on the bus while USB0 is in sus-
pend mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
0 SUSINT Suspend Interrupt-Pending Flag.
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by
hardware when Suspend signaling is detected on the bus. This bit is cleared when
software reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
Rev. 1.4
189
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