C8051F391 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F391' PDF : 300 Pages View PDF
C8051F39x/37x
4. Pin Definitions
Table 4.1. Pin Definitions for the C8051F39x/37x
Name
VDD
GND
RST/
C2CK
C2D
P0.0/
VREF
P0.1
IDA0
P0.2/
XTAL1
P0.3/
XTAL2
P0.4
P0.5
Pin
Pin
Pin
‘F392/3/6/ ’F390/1/ ’F370/1/
7/8/9
4/5
4/5
Type Description
3
4
4
Power Supply Voltage.
2
3
3
Ground.
This ground connection is required. The center
pad may optionally be connected to ground also.
4
5
5
D I/O Device Reset. Open-drain output of internal
POR or VDD monitor. An external source can ini-
tiate a system reset by driving this pin low for at
least 10 µs.
D I/O Clock signal for the C2 Debug Interface.
5
6
6
D I/O Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
1
2
2
D I/O or Port 0.0.
A In
A In External VREF input.
20
1
1
D I/O or Port 0.1.
A In
A Out IDA0 Output.
19
24
24 D I/O or Port 0.2.
A In
A In External Clock Input. This pin is the external
oscillator return for a crystal or resonator.
18
23
23 D I/O or Port 0.3.
A In
A I/O or External Clock Output. For an external crystal or
D In resonator, this pin is the excitation driver. This
pin is the external clock input for CMOS, capaci-
tor, or RC oscillator configurations.
17
22
22 D I/O or Port 0.4.
A In
16
21
21 D I/O or Port 0.5.
A In
22
Preliminary Rev. 0.71
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