C8051F97X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F97X

Low Power Capacitive Sensing MCU with up to 32 kB of Flash

Silicon Laboratories 

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Register 13.2. IP: Interrupt Priority

Bit

7

6

5

4

3

2

1

0

Name Reserved PSPI0

PT2

PS0

PT1

PX1

PT0

PX0

Type

R

RW

RW

RW

RW

RW

RW

RW

Reset

1

0

0

0

0

0

0

0

SFR Page = ALL; SFR Address: 0xB8 (bit-addressable)

Table 13.3. IP Register Bit Descriptions

Bit

Name

Function

7

Reserved Must write reset value.

6

PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.

This bit sets the priority of the SPI0 interrupt.

0: SPI0 interrupt set to low priority level.

1: SPI0 interrupt set to high priority level.

5

PT2

Timer 2 Interrupt Priority Control.

This bit sets the priority of the Timer 2 interrupt.

0: Timer 2 interrupt set to low priority level.

1: Timer 2 interrupt set to high priority level.

4

PS0

UART0 Interrupt Priority Control.

This bit sets the priority of the UART0 interrupt.

0: UART0 interrupt set to low priority level.

1: UART0 interrupt set to high priority level.

3

PT1

Timer 1 Interrupt Priority Control.

This bit sets the priority of the Timer 1 interrupt.

0: Timer 1 interrupt set to low priority level.

1: Timer 1 interrupt set to high priority level.

2

PX1

External Interrupt 1 Priority Control.

This bit sets the priority of the External Interrupt 1 interrupt.

0: External Interrupt 1 set to low priority level.

1: External Interrupt 1 set to high priority level.

1

PT0

Timer 0 Interrupt Priority Control.

This bit sets the priority of the Timer 0 interrupt.

0: Timer 0 interrupt set to low priority level.

1: Timer 0 interrupt set to high priority level.

0

PX0

External Interrupt 0 Priority Control.

This bit sets the priority of the External Interrupt 0 interrupt.

0: External Interrupt 0 set to low priority level.

1: External Interrupt 0 set to high priority level.

84

Rev 1.1

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