C8051F97X View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F97X' PDF : 455 Pages View PDF
In low power modes (low power active mode and low power idle mode) there are two mechanisms to provide
clocks to peripherals:
CPU turns on the clocks of peripherals through SFR registers. Examples of such peripherals are Timers,
PCA0, ADC0, etc.
Peripherals with clock request capability can request for the clocks when needed. Examples of such
peripherals are DMA0, I2C Slave, etc.
int req
Interrupt Module
int clk req int clk int
int
int req
Modules with
clock requesting
capability (I2C
Slave, etc.)
pclk req
pclk
int
Clock Generator
Modules without
clock requesting
capability (Timers,
PCA0, etc.)
DMA req
DMA clk req
DMA clk
CPU idle
CPU clk
DMA
CPU
Figure 16.1. C8051F97x Module Clocking in Low Power Modes
Modules that are capable of requesting for clocks can do so at any time. These modules will use the requested
clock to synchronize with outgoing DMA request or interrupt request. On the other hand, modules with no capability
of requesting for clocks will always receive clock from clock generation module if their clock sources are enabled
through t he PCLKEN register.
16.1. Normal Active Mode
The MCU is fully functional in normal active mode. Figure 16.2shows the on-chip power distribution to various
peripherals. There are two supply voltages powering various sections of the chip: VDD and the 1.8 V internal core
supply. All analog peripherals are directly powered from the VDD pin. All digital peripherals and the CIP-51 core are
powered from the 1.8 V internal core supply. RAM, PMU0 and the SmaRTClock are always powered directly from
the VDD pin in sleep mode and powered from the core supply in all other power modes.
95
Rev 1.1
Share Link: 
