C8051T600/1/2/3/4/5/6
SFR Definition 21.2. OSCICN: Internal H-F Oscillator Control
Bit
7
6
Name
Type
R
R
Reset
0
0
5
4
3
2
1
0
IFRDY CLKSL IOSCEN
IFCN[1:0]
R
R
R
R/W
R/W
0
1
0
1
0
0
SFR Address = 0xB2
Bit Name
Function
7:5 Unused Unused. Read = 000b; Write = Don’t Care
4
IFRDY Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
3
CLKSL System Clock Source Select Bit.
0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits.
1: SYSCLK derived from the External Clock circuit.
2 IOSCEN Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
1:0 IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
102
Rev. 1.2