C8051T601 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T601' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun-
ter/timer and load it into the corresponding module's 16-bit Capture/Compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
PCA0CPMn
PECCMT PE
WC A A A O WC
MO P P T GMC
1 MPN n n n F
6nnn
n
n
xx
000x
PCA Interrupt
PCA0CN
CC
CCC
FR
CCC
FFF
210
Port I/O
Crossbar CEXn
0
1
0
1
PCA0CPLn PCA0CPHn
Capture
PCA
Timebase
PCA0L
PCA0H
Figure 26.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least two system clock cycles to be recognized by the
hardware.
164
Rev. 1.2
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