C8051T602-GS View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T602-GS' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
Figure 7.2. QFN-10 PCB Land Pattern
Table 7.2. QFN-10 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
e
0.50 BSC.
X1
0.20
0.30
C1
1.70
1.80
Y1
0.85
0.95
C2
1.70
1.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.2
29
Share Link: 
