C8051T602 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T602' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
22. Port Input/Output
Digital and analog resources are available through eight I/O pins on the C8051T600/1/2/3/4/5, or six I/O
pins on the C8051T606. Port pins P0.0-P0.7 can be defined as general-purpose I/O (GPIO), assigned to
one of the internal digital resources, or assigned to an analog function as shown in Figure 22.1. Port pin
P0.7 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which
functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility
is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the P0 port latch, regardless of the crossbar settings.
The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.3 and Figure 22.4). The registers XBR1 and XBR2, defined in SFR Definition 22.2 and SFR
Definition 22.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Section “8. Electrical Characteristics” on page 30.
XBR0, XBR1,
XBR2 Registers
P0MDOUT,
P0MDIN Registers
Highest
Priority
Lowest
Priority
2
UART
Priority
Decoder
2
SMBus
CP0
2
Outputs
SYSCLK
Digital
Crossbar
8
PCA
4
2
T0, T1
8
Port Latch P0 (P0.0-P0.7)
P0
I/O
Cells
P0.0
(‘T600/1/2/3/4/5 Only)
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
(‘T600/1/2/3/4/5 Only)
P0.7
To Analog Peripherals
(ADC0, CP0, VREF, EXTCLK)
Figure 22.1. Port I/O Functional Block Diagram
106
Rev. 1.2
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