C8051T603 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051T603' PDF : 168 Pages View PDF
C8051T600/1/2/3/4/5/6
23.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated
and the ACKRQ bit is set. The software must respond to the received slave address with an ACK or ignore
the received slave address with a NACK.
If the received slave address is ignored by software (by NACKing the address), slave interrupts will be
inhibited until the next START is detected. If the received slave address is acknowledged, zero or more
data bytes are received.
The ACKRQ bit is set to 1 and an interrupt is generated after each received byte. Software must write the
ACK bit at that time to ACK or NACK the received byte.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 23.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte transferred’ interrupts occur before the ACK.
S
SLA
WA
Data Byte
A
Data Byte
AP
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt Locations
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Figure 23.7. Typical Slave Write Sequence
Rev. 1.2
133
Share Link: 
