CAM35C44 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'CAM35C44' PDF : 50 Pages View PDF
DRQ_LEV, Bit 0
CR02 - Infrared Option
The DRQ_LEV bit D0 determines the active
state of the DMA Request (DRQ) output pin
(TABLE 1).
If DRQ_LEV is “0” (default), the DRQ pin is
active low. If DRQ_LEV is “1”, the DRQ pin is
active high.
DAC_LEV, Bit 1
The DAC_LEV bit D1 determines the active state
of the DMA Acknowledge (DACK) input pin
(TABLE 1).
If DAC_LEV is “0” (default), the DACK pin is
active low. If DAC_LEV is “1”, the DACK pin is
active high.
The Infrared Option register CR02 determines
the infrared port transmit and receive pin
polarity, the port duplex mode, and the infrared
port protocol.
The controls in the Infrared Option register are
also duplicated in the IrCC 2.0 SCE
Configuration Register A. These controls are
arranged such that the last write from either
source determines the current control state and
is visible in both registers.
CR02 can only be accessed in the configuration
state and only after the CSR has been initialized
to 02H. The default value of this register after
power up is 02H (TABLE 16).
Bits[7:6] in the Infrared Option register are
RESERVED.
TABLE 16 - INFRARED OPTION REGISTER
D7 D6
D5
D4
D3
D2
D1
D0 DEFAULT
IR_
IR_
IR_
HALF
XMT_ RCV_
CR02 R/W
RES.
MODE2 MODE1 MODE0 DUPLEX POL
POL
0x02
RCV_POL, Bit 0
XMT_POL, Bit 1
The RCV_POL bit D0 defines the active state for
the infrared port receive pins.
The XMT_POL bit D1 defines the active state for
the infrared port transmit pins.
If RCV_POL is “0” (default), the IRRX pin is
active low. If RCV_POL is “1”, the IRRX pin is
active high.
If XMT_POL is “0”, the IRTX pin is active low. If
XMT_POL is “1” (default), the IRTX pin is active
high.
The RCV_POL pin has no affect when the port is
configured as a 16C550A UART (see section
IR_MODE, Bits 3 - 5 on page 24).
The XMT_POL pin has no affect when the port is
configured as a 16C550A UART (see section
IR_MODE, Bits 3 - 5 on page 24).
23
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