Write Cycle Timing (Non-Multiplexed)
SA[4:0]
t5
nCS
nWR
t3
t1
t4
t2
SD[7:0]
FIGURE 12 - WRITE CYCLE (NON-MULTIPLEXED ADDRESS AND DATA)
TABLE 38 - WRITE CYCLE TIMING PARAMETERS (NON-MULTIPLEXED ADDRESS AND DATA)
NAME
DESCRIPTION
MIN
TYP MAX UNITS
t1
Chip Select and Address Valid to Write Pulse
23
ns
Active
t2
Data Hold Time
8
ns
t3
Write Pulse Width
85
ns
t4
Data valid to Write Pulse Inactive
30
ns
t5
Write Pulse Active to Chip Select and Address
15
ns
Note 1 Invalid
Note 1: Chip select must be latched internally and released when write pulse goes inactive.
41