CC1110F16RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC1110F16RSPR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC1110F16RSPR' PDF : 240 Pages View PDF
to flash memory takes place each time two
bytes have been written to FWDATA, meaning
that the number of bytes written to flash must
be a multiple of two.
0x7FFE
0x7C00
0x0BFE
0x0800
0x03FE
0x0000
PAGE 32
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0x7FFF
0x7C01
0x0BFF
0x0801
0x03FF
0x0001
Figure 19: Flash Address (in unified memory
space)
When accessed by the Flash Controller, the
flash memory is word-addressable. Each page
in flash consists of 512 words, addressed
through
FADDRH[0]:FADDRL[7:0].
FADDRH[5:1] is used to indicate the page
number. That means that if one wants to write
to the byte in flash mapped to address
0x0BFE, FADDRH:FADDRL should be 0x05FF
(page 2, word 511).
The CPU will not be able to access the flash,
e.g. to read program code, while a flash write
operation is in progress. Therefore the
program code executing the flash write must
be executed from RAM, meaning that the
program code must reside in the area starting
from address 0xF000 in CODE memory space
(unified) and not exceed maximum range for
device in use (F8, F16, or F32). When using the
DMA to write to flash, the code can be
executed from within flash memory.
CC1110Fx / CC1111Fx
When a flash write operation is executed from
RAM, the CPU continues to execute code from
the next instruction after initiation of the flash
write operation (FCTL.WRITE=1).
The FCTL.SWBSY bit must be 0 before
accessing the flash after a flash write,
otherwise an access violation occurs. This
means that FCTL.SWBSY must be 0 before
program execution can continue from a
location in flash memory.
13.3.2.1 DMA Flash Write
When using the DMA to write to flash, the data
to be written is stored in the XDATA memory
space (RAM or flash). A DMA channel should
be configured to have the location of the stored
data as source address and the Flash Write
Data register, FWDATA, as the destination
address. The DMA trigger event FLASH
should be selected (TRIG[4:0]=10010).
Please see section 13.5 for more details
regarding DMA operation. Thus the Flash
Controller will trigger a DMA transfer when the
Flash Write Data register, FWDATA, is ready to
receive new data.
When the DMA channel is armed, starting a
flash write by setting FCTL.WRITE to 1 will
trigger the first DMA transfer.
Figure 20 shows an example on how a DMA
channel is configured and how a DMA transfer
is initiated to write a block of data from a
location in XDATA to flash memory.
The DMA channel should be configured to
operate in single transfer mode, the transfer
count should be equal the size of the data
block to be transferred (must be a multiple of
2), and each transfer should be a byte. Source
address should be incremented by one for
each transfer, while the destination address
should be fixed.
SWRS033E
Page 86 of 239
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